Image processing apparatus and method and program of the same

ABSTRACT

An image processing apparatus capable of flexibly changing edge enhancement, blurring, and other image effect processing, wherein, in accordance with the execution of a program by a CPU, the CPU produces control signals to control an image processing circuit, read circuits in the image processing circuit read image data from a memory circuit by using a texture function, a write circuit writes the image data produced by subtraction by a subtraction circuit, multiplication with a coefficient by a multiplication circuit, and addition by an addition circuit to the memory circuit, and the image processing circuit performs processing relating to image effects such as α-blending, edge enhancement, and blurring on the basis of the control signals from the CPU.

This is a continuation of application Ser. No. 10/184,928, filed Jul. 1,2002, the entire contents of which are hereby incorporated by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to an image processing apparatus andmethod and program of the same capable of flexibly changing α-blending,edge enhancement, blurring, and other image processing.

2. Description of the Related Art

Computer aided design (CAD) systems, amusement apparatuses, etc. includebuilt-in rendering circuits for computer graphic processing.

These rendering circuits use exclusive hardware for the edgeenhancement, blurring, and other image processing on the displayedimages.

Since the rendering circuits perform edge enhancement, blurring, andother image processing by using exclusive hardware, there is thedisadvantage that the edge enhancement, blurring, and other effectscannot be flexibly changed.

SUMMARY OF THE INVENTION

An object of the present invention is to provide an image processingapparatus and method and program of the same capable of flexiblychanging the edge enhancement, blurring, and other image effectprocessing.

To attain the above object, according to a first aspect of the presentinvention, there is provided an image processing apparatus comprising amemory circuit for storing image data; a read circuit for reading atleast first image data, second image data, and third image data from thememory circuit; a first processing circuit for producing fourth imagedata indicating a difference between the first image data and the secondimage data read by the read circuit; a second processing circuit formultiplying the fourth image data with a predetermined coefficient toproduce fifth image data; a third processing circuit for adding thethird image data and the fifth image data to produce sixth image data; awrite circuit for writing the sixth image data to the memory circuit;and a control circuit for executing a predetermined program to controlthe read circuit, the first processing circuit, the second processingcircuit, the third processing circuit, and the write circuit inaccordance with execution of the program.

The operation of the first aspect of the present invention is asfollows.

The control circuit executes the program to control the followingprocessing in accordance with the execution of the program.

First, the read circuit reads first image data and second image datafrom the memory circuit.

Then, the first processing circuit generates fourth image dataindicating a difference between the first image data and the secondimage data.

Then, the second processing circuit multiplies the fourth image datawith a predetermined coefficient to produce fifth image data.

Further in parallel with the processing of the second processingcircuit, the read circuit reads third image data from the memorycircuit.

Then, the third processing circuit adds the third image data and thefifth image data to produce sixth image data.

Then, a write circuit writes the fifth image data in the memory circuit.

According to a second aspect of the present invention, there is provideda method of image processing comprising a first step of producing fourthimage data indicating a difference between first image data and secondimage data; a second step of multiplying the fourth image data with apredetermined coefficient to produce fifth image data; and a third stepof adding the third image data and the fifth image data to produce sixthimage data, executing a predetermined program, and controlling the firstto third steps in accordance with the execution of the program.

According to a third aspect of the present invention, there is provideda program executed by a processing apparatus to control a firstprocessing circuit, a second processing circuit, and a third processingcircuit comprising a first routine of producing fourth image dataindicating a difference between first image data and second image databy the first processing circuit; a second routine of multiplying thefourth image data with a predetermined coefficient to produce fifthimage data by the second processing circuit; and a third routine ofadding the third image data and the fifth image data to produce sixthimage data by the third processing circuit.

BRIEF DESCRIPTION OF THE DRAWINGS

These and other objects and features of the present invention willbecome clearer from the following description of the preferredembodiments given with reference to the attached drawings, in which:

FIG. 1 is a view of the configuration of an image processing apparatusof the present embodiment;

FIG. 2 is a view for explaining a case of α-blending using the imageprocessing apparatus shown in FIG. 1;

FIG. 3 is a view for explaining another case of α-blending using theimage processing apparatus shown in FIG. 1;

FIG. 4 is a view for explaining a case of edge enhancement using theimage processing apparatus shown in FIG. 1;

FIG. 5 is a view for explaining the effects of the edge enhancementshown in FIG. 4;

FIG. 6 is another view for explaining the effects of the edgeenhancement shown in FIG. 4;

FIG. 7 is a view for explaining the case of blurring by averaging valuesof four pixels using the image processing apparatus shown in FIG. 1;

FIG. 8 is a view for explaining an example of an operation when theimage processing apparatus shown in FIG. 1 performs processingcorresponding to “image IM_(—)12a×½+(1½)×image IM_(—)12” in equation(3);

FIG. 9 is a view for explaining an example of an operation when theimage processing apparatus shown in FIG. 1 performs processingcorresponding to “image IM_(—)12b×⅓+(1⅓)×{image IM_(—)12a×1/2+(1½)×image IM_(—)12}” in equation (3) using a result of theprocessing “image IM_(—)12a×½+(1½)×image IM_(—)12” shown in FIG. 8;

FIG. 10 is a view for explaining an example of an operation when theimage processing apparatus shown in FIG. 1 performs processingcorresponding to equation (3) using the result of the processing “imageIM_(—)12b×⅓+(1⅓)×{image IM_(—)12a×½+(1½)×image IM _(—)12}” shown in FIG.9; and

FIG. 11 is a view for explaining a case of blurring by averaging thevalues of nine pixels using the image processing apparatus shown in FIG.1.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

Below, embodiments of an image processing apparatus of the presentinvention will be explained.

FIG. 1 is a view of the configuration of an image processing apparatus 1of the present embodiment.

As shown in FIG. 1, the image processing apparatus 1 comprises a CPU 2,a memory 3, and an image processing circuit 4.

The image processing apparatus 1 corresponds to the image processingapparatus of the present invention, the CPU 2 corresponds to the controlcircuit of the present invention, and the memory 3 corresponds to thememory circuit of the present invention.

CPU 2

The CPU 2 produces control signals S2 a, S2 b, S2 c, S2 d, S2 e, S2 f,and S2 g, described later, to be output to a read circuit 10, a readcircuit 11, a write circuit 18, a selector 12, a selector 13, a selector14, and a multiplication circuit 16.

The CPU 2 executes a predetermined program to produce the controlsignals mentioned above in accordance with the execution of the program.

The memory 3 stores various image data (for example, texture data) to beused for a processing of the image processing circuit 4 so that theimage data may be read by specifying a read position by pixel unitsusing coordinate data (u, v).

Image Processing Circuit 4

The image processing circuit 4, as shown in FIG. 1, comprises, forexample, the read circuits 10 and 11, the selectors 12, 13, and 14, thesubtraction circuit 15, the multiplication circuit 16, the additioncircuit 17, and the write circuit 18.

Here, the read circuits 10 and 11 correspond to the read circuit of thepresent invention, the selectors 12, 13, 14 correspond to the selectingcircuit of the present invention, the subtraction circuit 15 correspondsto the first processing circuit of the present invention, themultiplication circuit 16 corresponds to the second processing circuitof the present invention, and the addition circuit 17 corresponds to thethird processing circuit of the present invention.

The read circuit 10 reads image data S3 a (first image data and thirdimage data of present invention) from the memory 3 in units of pixeldata by using coordinate data (u,v) of the image designated by a controlsignal S2 a when reading image data from the memory 3 on the basis ofthe control signal S2 a from the CPU 2.

Further, the read circuit 10 reads the image data S3 a from an addressof the memory 3 designated by the control signal S2 a from the CPU 3.

The read circuit 10 outputs the image data S3 a read from the memory 3to first input terminals of the selectors 12, 13, and 14.

The read circuit 11 reads image data S3 b (second image data and thirdimage data of present invention) from the memory 3 in units of pixeldata by using coordinate data (u,v) of the image designated by a controlsignal S2 b when reading image data from the memory 3 on the basis ofthe control signal S2 b from the CPU 2.

Further, the read circuit 11 reads image data S3 b from an address ofthe memory 3 designated by the control signal S2 b from the CPU 3.

The read circuit 11 outputs the image data S3 b read from the memory 3to second input terminals of the selectors 12, 13, and 14.

The selector 12 selects one of the image data S3 a input from a firstinput terminal and the image data S3 b input from a second inputterminal on the basis of the control signal S2 d from the CPU 2 andoutputs the selected image data to the subtraction circuit 15.

The selector 13 selects one of the image data S3 a input from a firstinput terminal and the image data S3 b input from a second inputterminal on the basis of the control signal S2 e from the CPU 2 andoutputs the selected image data to the subtraction circuit 15.

The selector 14 selects one of the image data S3 a input from a firstinput terminal and the image data S3 b input from a second inputterminal on the basis of the control signal S2 f from the CPU 2 andoutputs the selected image data to the addition circuit 17.

The subtraction circuit 15 subtracts the image data input from theselector 13 from the image data input from the selector 12 to produceimage data S15 (fourth image data of present invention) and outputs theimage data S15 to the multiplication circuit 16.

The subtraction of the subtraction circuit 15 is performed, for example,by using the values of R, G, and B (pixel values) indicated by the pixeldata for each of the pixel data which constitute the image data.

The multiplication circuit 16 multiplies the image data S15 with acoefficient indicated by the control signal S2 g input from the CPU 2 toproduce image data S16 (fifth image data of present invention) andoutputs the image data S16 to the addition circuit 17.

The multiplication of the multiplication circuit 16 is performed, forexample, by multiplying each of the image data constituting the imagedata S15 with the coefficient indicated by the control signal S2 g.

The addition circuit 17 adds the image data S16 input from themultiplication circuit 16 and the image data input from the selector 14to produce image data S17 (sixth image data of present invention) andoutputs the image data S17 to the write circuit 18.

The addition of the addition circuit 17 is performed, for example, byusing the values of R, G, and B indicated by the pixel data for each ofthe pixel data constituting the image data.

The write circuit 18 writes the image data S17 input from the additioncircuit 17 to the address in the memory 3 designated by the controlsignal S2 c from the CPU 2.

Below, examples of the operation of the image processing apparatus 1shown in FIG. 1 will be explained.

FIRST EXAMPLE OF OPERATION

Below, an example of the operation of the case of α-blending using theimage processing apparatus 1 will be explained.

Here, an example of α-blending between an image IM_1 and an image IM_2with a coefficient α will be explained referring to FIG. 2.

In this case, the read circuit 10 shown in FIG. 1 reads the image dataS3 a of the image IM_1 shown in FIG. 2 from the memory 3, and theselector 12 selects the image data S3 a and outputs it to thesubtraction circuit 15.

In parallel with this, the read circuit 11 shown in FIG. 1 reads theimage data S3 b of the image IM_2 shown in FIG. 2 from the memory 3, andthe selector 13 selects the image data S3 b and outputs it to thesubtraction circuit 15.

Then, the subtraction circuit 15 subtracts the image data S3 b from theimage data S3 a, that is, subtracts the image IM_2 from the image IM_1,and then outputs the resultant image data S16 to the addition circuit17.

Then, the multiplication circuit 16 multiplies the image data S15 by thecoefficient a designated by the control signal S2 g and then outputs theresultant image data S16 to the addition circuit 17.

Further, in parallel with the processing of the multiplication circuit16, the read circuit 11 shown in FIG. 1 reads the image data S3 b of theimage IM_2 shown in FIG. 2 from the memory 3, and then the selector 14selects the image data S3 b and outputs it to the addition circuit 17.

Then, the addition circuit 17 adds the image data S16 from themultiplication circuit 16 and the image data S3 b from the selector 14to produce the image data S17 of an image IM_3 blending the image IM_1and the image IM_2.

Then, the write circuit 18 writes the image data S17 to the memory 3.

The α-blending of the image processing apparatus 1 described above isshown in the following equation (1). Equation (1) may be modified togive an equation of general α-blending as shown in the followingequation (2).(image IM_1−image IM_2)×α+image IM_2 (1)α×IM_1+(1=α-IM_2   (2)

FIG. 2 shows an example of α-blending the image IM_1 of a heart and theimage IM_2 of an arrow. The image shown in FIG. 3 is obtained when usingthe image IM_1 of the letter “B” and the image IM_2 of the letter “A”.

SECOND EXAMPLE OF OPERATION

Below, an example of the operation of the case of edge enhancement usingthe image processing apparatus 1 will be explained.

In this case, the read circuit 10 shown in FIG. 1 reads the image dataS3 a of the image IM_12 of the letter “A” shown in FIG. 4 from thememory 3, and the selector 12 selects the image data S3 a and outputs itto the subtraction circuit 15.

In parallel with this, the read circuit 11 shown in FIG. 1 reads theimage data S3 b of the image IM_12 a obtained by shifting the imageIM_12 of the letter “A” shown in FIG. 4 to the right direction by onepixel from the memory 3, and the selector 13 selects the image data S3 band outputs it to the subtraction circuit 15.

In this case, the read operation of the image data S3 b of the imageIM_12 a by the read circuit 11 is performed by using coordinate data(u,v) of the texture image of the letter “A” stored in the memory 3.That is, the read circuit 11 reads the image IM_12 a obtained byshifting the image IM_12 by one pixel to the right direction by using afunction of texture mapping. Then, the subtraction circuit 15 subtractsthe image data S3 b from the image data S3 a, that is, subtracts theimage IM_12 a from the image IM_12, and then outputs the resultant imagedata S15 to the multiplication circuit 16.

Then, the multiplication circuit 16 multiplies the image data S15 withthe coefficient α(=½) designated by the control signal S2 g and outputsthe resultant image data S16 to the addition circuit 17. The coefficientα is determined in accordance with the degree of the edge enhancement.

Further, in parallel with the processing of the multiplication circuit16, the read circuit 11 shown in FIG. 1 reads the image data S3 a of theimage IM_12 from the memory 3, and the selector 14 selects the imagedata S3 b and outputs it to the addition circuit 17.

Then, the addition circuit 17 adds the image data S16 from themultiplication circuit 16 and the image data S3 a from the selector 14to produce the image data S17 and then outputs it to the write circuit18.

Then, the write circuit 18 writes the image data S17 to the memory 3.

Below, the operation and effects of the edge enhancement of the imageprocessing apparatus 1 explained by using FIG. 4 will be explained.

As shown in FIG. 5, when viewing the pixel values (R, G, and B values)of the pixel data on line 50 of the image IM_12 shown in FIG. 4, thelevels of the pixel values become, for example, as shown in FIG. 6A.

Further, the pixel values of the pixel data on line 50 of the imageIM_12 a obtained by shifting the image IM_12 by one pixel to the rightdirection become as shown in FIG. 6B.

Further, the pixel values on line 50 of the image data Si 5 obtained bysubtracting the pixel values of the image IM_12 a shown in FIG. 6B fromthe pixel values of the image IM_12 shown in FIG. 6A become as shown inFIG. 6C.

Further, the pixel values on line 50 of the image S16 resulting frommultiplying the pixel values of FIG. 6C with a become as shown in FIG.6D.

Then, the pixel values on line 50 of the image S17 resulting from addingthe pixel values of FIG. 6A to the pixel values of FIG. 6D become asshown in FIG. 6E. As shown in FIG. 6E, it is understood that the imageIM_13 shown in FIG. 4 becomes an edge enhanced image.

THIRD EXAMPLE OF OPERATION

Below, an example of the operation of the image processing apparatus 1when performing filtering used for blurring an image, suppressingglittering due to the aliasing component at the time of compressing animage, and suppressing the mosaic at the time of enlarging it will beexplained.

For example, as shown in FIG. 7, an example of filtering for averagingpixel values of four adjacent pixels P, P_a, P_b, and P_c to produce ablurred image will be explained.

In this case, when considering filtering with respect to the image IM_12of the letter “A” explained using FIG. 4, if the image obtained byshifting the image IM_12 by one pixel to the right direction isdesignated as the image IM_12 a, the image obtained by shifting theimage IM_12 by one pixel to the right direction and by one pixel to thelower direction is designated as the image IM_12 b, and the imageobtained by shifting the image IM_12 by one pixel to the lower directionis designated as the image IM_12 c, the image processing apparatus 1filters these images based on the following equation (3):image IM_12×¼+image IM_12 a×¼+image IM_12b×¼+image IM_12 c×¼=image IM_12 c×¼+(1¼)×[image IM_12 b×⅓+(1⅓)×{imageIM_12 a×½+(1½)×image IM_12}  (3)

The image processing apparatus 1 performs processing corresponding toequation (3) as shown in FIG. 8 to FIG. 10.

FIG. 8 is a view for explaining an example of the operation whenperforming processing corresponding to “image IM_(—)12a×½+(1½)×imageIM_(—)12” in equation (3).

FIG. 9 is a view for explaining an example of operation when performingprocessing corresponding to “image IM_(—)12b×⅓+(1⅓)×{imageIM_(—)12a×½+(1½)×image IM_(—)12}” in equation (3) using a result of theprocessing “image IM_(—)12a×½+(1½)×image IM_(—)12” shown in FIG. 8.

FIG. 10 is a view for explaining an example of the operation whenperforming processing corresponding to equation (3) using the result ofthe processing “image IM_(—)12b×⅓+(1⅓)×{image IM_(—)12a×½+(1½)×imageIM_(—)12}” shown in FIG. 9.

Below, an example of the operation of the image processing apparatus 1when performing the processing shown in FIG. 8 and FIG. 9 will beexplained.

First, in the image processing apparatus 1, as shown in FIG. 8, the readcircuit 10 shown in FIG. 1 reads the image data S3 a of the image IM_12a obtained by shifting the image IM_12 of the letter “A” by one pixel tothe right direction from the memory 3, while the selector 12 selects theimage data S3 a and outputs it to the subtraction circuit 15.

At this time, the read operation of the image data S3 a of the imageIM_12 a by the read circuit 10 is performed using the coordinate data(u,v) of the image (for example, texture image) of the letter “A” storedin the memory 3 on the basis of the control signal S2 a from the CPU 2.That is, the read circuit 11 reads the image IM_12 a obtained byshifting the image IM_12 by one pixel to the right direction from thememory 3 using the texture mapping function.

In parallel with this, the read circuit 11 shown in FIG. 1 reads theimage data S3 b of the image IM_12 of the letter “A” from the memory 3,and then the selector 13 selects the image data S3 b and outputs it tothe subtraction circuit 15.

Then, the subtraction circuit 15 subtracts the image data S3 b from theimage data S3 a, that is, subtracts the image IM_12 from the image IM_12a, and then outputs the resultant image data S15 to the multiplicationcircuit 16.

Then, the multiplication circuit 16 multiplies the image data S15 withthe coefficient a (=½) indicated by the control signal S2 g and thenoutputs the resultant image data S15 to the addition circuit 17.

Further, in parallel with the processing of the multiplication circuit16, the read circuit 11 shown in FIG. 1 reads the image data S3 b of theimage IM_12 shown in FIG. 4 from the memory 3, and the selector 14selects the image data S3 b and outputs it to the addition circuit 17.

Then, the addition circuit 17 adds the image data S16 from themultiplication circuit 16 and the image data S3 b from the selector 14to produce the image data S17 of the image IM_31 corresponding to theresult of the processing “image IM_(—)12a×½+(1½)×image IM_(—)12” ofequation (3) and outputs the image data S17 to the write circuit 18.

Then, the write circuit 18 writes the image data S17 to an address inthe memory 3 designated by the control signal S2 g.

Next, in the image processing apparatus 1, as shown in FIG. 9, the readcircuit 10 shown in FIG. 1 reads the image data S3 a of the image IM_12b obtained by shifting the image IM_12 of the letter “A” by one pixel inthe right direction and a lower direction from the memory 3, and theselector 12 selects the image data S3 a and outputs it to thesubtraction circuit 15.

At this time, the read operation of the image data S3 a of the imageIM_12 b by the read circuit 10 is performed by using the coordinate data(u,v) of the image of the letter “A” stored in the memory 3 on the basisof the control signal S2 a from the CPU 2. That is, the read circuit 11reads the image IM_12 b obtained by shifting the image IM_12 by onepixel in the right direction and a lower direction from the memory 3 byusing the texture mapping function.

In parallel with this, the read circuit 11 shown in FIG. 1 reads theimage data S3 b of the image IM_31 explained using FIG. 8, and theselector 13 selects the image data S3 b and outputs it to thesubtraction circuit 15.

Then, the subtraction circuit 15 subtracts the image data S3 b from theimage data S3 a, that is, subtracts the image IM_31 from the image IM_12b, and then outputs the resultant image data S15 to the multiplicationcircuit 16.

Then, the multiplication circuit 16 multiplies the image data S15 withthe coefficient a (=⅓) indicated by the control signal S2 g and thenoutputs the resultant image data S16 to the addition circuit 17.

Further, in parallel with the processing of the multiplication circuit16, in a way similar to the operation described above, the read circuit11 shown in FIG. 1 reads the image data S3 b of the image IM_31 shown inFIG. 8 from the memory 3, and the selector 14 selects the image data S3b and outputs it to the addition circuit 17.

Then, the addition circuit 17 adds the image data S16 from themultiplication circuit 16 and the image data S3 b from the selector 14to produce the image data S17 of the image IM_32 corresponding to theresult of the processing “image IM_(—)12a×½+(1½)×image IM_(—)12” ofequation (3) and outputs the image data S17 to the write circuit 18.

Then, the write circuit 18 writes the image data S17 to an address ofthe memory 3 designated by the control signal S2 g.

Next, in the image processing apparatus 1, as shown in FIG. 10, the readcircuit 10 shown in FIG. 1 reads the image data S3 a of the image IM_12c obtained by shifting the image IM_12 of the letter “A” by one pixel inthe lower direction from the memory 3, and the selector 12 selects theimage data S3 a and outputs it to the subtraction circuit 15.

At this time, the read operation of the image data S3 a of the imageIM_12 c by the read circuit 10 is performed by using the coordinate data(u,v) of the image of the letter “A” stored in the memory 3 on the basisof the control signal S2 a from the CPU 2. That is, the read circuit 11reads the image IM_12 c obtained by shifting the image IM_12 by onepixel in the lower direction from the memory 3 by using the texturemapping function.

In parallel with this, the read circuit 11 shown in FIG. 1 reads theimage data S3 b of the image IM_32 from the memory 3, and then theselector 13 selects the image data S3 b and outputs it to thesubtraction circuit 15.

Then, the subtraction circuit 15 subtracts the image data S3 b from theimage data S3 a, that is, subtracts the image IM_32 from the image IM_12c, and then outputs the resultant image data S15 to the multiplicationcircuit 16.

Then, the multiplication circuit 16 multiplies the image data S15 withthe coefficient a (=¼) indicated by the control signal S2 g and thenoutputs the resultant image data S16 to the addition circuit 17.

Further, in parallel with the processing of the multiplication circuit16, the read circuit 11 shown in FIG. 1 reads the image data S3 b of theimage IM_32 shown in FIG. 8 from the memory 3, and the selector 14selects the image data S3 b and outputs it to the addition circuit 17.

Then, the addition circuit 17 adds the image data S16 from themultiplication circuit 16 and the image data S3 b from the selector 14to produce the image data S17 of the image IM_33 corresponding to theresult of the processing of equation (3) and outputs the image data S17to the write circuit 18.

Then, the write circuit 18 writes the image data S17 to an address inthe memory 3 designated by the control signal S2 g.

As described above, according to the image processing apparatus 1, it ispossible to flexibly perform various processing such as α-blending, edgeenhancement, and blurring of images, as described above, by having theCPU 2 control the read circuits 10 and 11, the write circuit 18, theselectors 12 to 14, and the multiplication circuit 16 on the basis ofcontrol signals S2 a to S2 g produced in accordance with the executionof the program.

That is, according to the image processing apparatus 1, it is possibleto easily change the control signals S2 a to S2 g produced by the CPU 2to change the content of the processing just by changing the programwithout changing the hardware configuration.

The present invention is not limited to the above described embodiment.

For example, in the embodiment shown in FIG. 7, an example of filteringfor producing blurred images by averaging the values of pixels of fouradjacent pixels P, P_a, P_b, and P_c was illustrated, but the imageprocessing apparatus 1 also may produce blurred images by processingbased on the following equation (4) when weighting nine adjacent orneighboring pixels P_A, P_B, P_C, P_D, P_E, P_F, P_G, P_H, and P_, asshown in FIG. 11.

In equation (4), the image IM_A is the original image, the image IM_B isan image obtained by shifting the image IM₁₃ A by one pixel to the rightdirection, the image IM_C is an image obtained by shifting the imageIM_A by two pixels to the right direction, the image IM_D is an imageobtained by shifting the image IM_A by one pixel to the lower direction,the image IM_E is an image obtained by shifting the image IM_A by onepixel to the right direction and the lower direction, the image IM_F isan image obtained by shifting the image IM_A by two pixels to the rightdirection and by one pixel to the lower direction, the image IM_G is animage obtained by shifting the image IM_A by two pixels to the lowerdirection, and the image IM_H is an image obtained by shifting the imageIM_A by two pixels to the right direction and lower direction.4/16×IM _(—) A+(1 4/16)×( 2/12IM _(—) B+(1 2/12)×( 2/10×IM _(—) C+(1 2/10)×( 2/8×IM _(—) D+(1 2/8)×( 2/6×IM _(—) E+(12/6)×(¼×IM _(—) F+(1¼)×(⅓×IM _(—) G+(1⅓)×(½×IM _(—) H+(1½)×IM _(—)I))))))))   (4)

Further, in the embodiment described above, an example of using theimage processing apparatus 1 for α-blending, edge enhancement, andblurring was described, but the image processing apparatus 1 may performother image processing as well by using the configuration shown in FIG.1.

Summarizing the effects of the invention, as explained above, accordingto the present invention, it is possible to provide an image processingapparatus capable of flexibly changing edge enhancement, blurring, andother image effect processing.

While the invention has been described with reference to specificembodiments chosen for purpose of illustration, it should be apparentthat numerous modifications could be made thereto by those skilled inthe art without departing from the basic concept and scope of theinvention.

The present disclosure relates to subject matter contained in JapanesePatent Application No. 2001-203336, filed on Jul. 4, 2001, thedisclosure of which is expressly incorporated herein by reference in itsentirety.

1. An image processing apparatus comprising: a memory circuit forstoring image data; a read circuit for reading at least first imagedata, second image data, and third image data from said memory circuit;a first processing circuit for producing fourth image data indicating adifference between said first image data and said second image data readby said read circuit; a second processing circuit for multiplying saidfourth image data with a predetermined coefficient to produce fifthimage data; a third processing circuit for adding said third image dataand said fifth image data to produce sixth image data; a write circuitfor writing said sixth image data to said memory circuit; and a controlcircuit for executing a predetermined program to control said readcircuit, said first processing circuit, said second processing circuit,said third processing circuit, and said write circuit in accordance withthe execution of said program; wherein said read circuit reads pluralimage data in parallel.
 2. The image processing apparatus as set forthin claim 1, wherein said read circuit comprises plural read circuits forrespectively reading image data in parallel.
 3. The image processingapparatus as set forth in claim 1, wherein said plural image datacomprises said first image data and said second image data.
 4. The imageprocessing apparatus as set forth in claim 1, wherein said read circuitreads one image data stored in said memory circuit as said first imagedata and said third image data and reads another image data as saidsecond image data; and said second processing circuit multiplies saidfourth image data with an α-blending coefficient as said predeterminedcoefficient to produce said fifth image data.
 5. The image processingapparatus as set forth in claim 3, wherein said read circuit readssingle image data stored in said memory circuit as said first image dataand said third image data from a predetermined read position from saidmemory circuit and reads said second data corresponding to an imageobtained by shifting an image corresponding to said single image data byone pixel to a predetermined direction; said first processing circuitproduces a difference between said first image data and said secondimage data read by said read circuit; said second processing circuitmultiplies said difference with a value corresponding to a degree ofedge enhancement; and said third processing circuit adds a result of themultiplication and said third image data to produce edge enhanced imagedata.
 6. The image processing apparatus as set forth in claim 3, whereinsaid read circuit reads image data stored in said memory circuit aplurality of times on the basis of said coordinate data while shiftingread positions by one pixel; and said control circuit performs controlto combine processing of said first processing circuit, said secondprocessing circuit, and said third processing circuit and average theplurality of image data obtained by the plurality of the read operationsto produce image data of an image blurring an image corresponding toimage data stored in said memory circuit.
 7. The image processingapparatus as set forth in claim 6, wherein said read circuit reads imagedata stored in said memory circuit from a predetermined position, readsthe image data from a position shifted from said predetermined positionby one pixel to the right direction, reads the image data from aposition shifted from said predetermined position by one pixel to thelower direction, and reads the image data from a position shifted fromsaid predetermined position by one pixel to the right direction and thelower direction; and said control circuit performs control to averagethe four series of image data read from the four read positions toproduce image data of an image blurring an image corresponding to imagedata read from said predetermined read position by the operations ofsaid first processing circuit, said second processing circuit, and saidthird processing circuit.
 8. The image processing apparatus as set forthin claim 1, wherein said control circuit performs control to combineoperations of said first processing circuit, said second processingcircuit, and said third processing circuit and performs processing whilegiving predetermined weights to said plurality of image data to produceimage data of an image blurring an image corresponding to image datastored in said memory circuit.
 9. A method of image processingcomprising: a first step of producing fourth image data indicating adifference between first image data and second image data; a second stepof multiplying said fourth image data with a predetermined coefficientto produce fifth image data; and a third step of adding said third imagedata and said fifth image data to produce sixth image data and executinga predetermined program and controlling said first to third steps inaccordance with the execution of said program.
 10. A program executed bya processing apparatus and controlling a first processing circuit, asecond processing circuit, and a third processing circuit, comprising: afirst routine of producing fourth image data indicating a differencebetween first image data and second image data by said first processingcircuit; a second routine of multiplying said fourth image data with apredetermined coefficient to produce fifth image data by said secondprocessing circuit; and a third routine of adding said third image dataand said fifth image data to produce sixth image data by said thirdprocessing circuit.
 11. A method of image processing comprising: a firststep of reading first image data and second image data from a memorycircuit in parallel; a second step of producing fourth image dataindicating a difference between said first image data and said secondimage data; a third step of multiplying said fourth image data with apredetermined coefficient to produce fifth image data; a fourth step ofreading third image data from said memory circuit; and a fifth step ofadding said third image data and said fifth image data to produce sixthimage data and executing a predetermined program and controlling saidfirst to third steps in accordance with the execution of said program.12. The method as set forth in claim 11, wherein said fourth step isoperated in parallel with said third step.
 13. A program executed by aprocessing apparatus and controlling a memory circuit, a read circuit, afirst processing circuit, a second processing circuit, and a thirdprocessing circuit, comprising: a first routine of reading first imagedata and second image data from said memory circuit in parallel by saidread circuit; a second routine of producing fourth image data indicatinga difference between said first image data and said second image data bysaid first processing circuit; a third routine of multiplying saidfourth image data with a predetermined coefficient to produce fifthimage data by said second processing circuit; a fourth routine ofreading third image data from said memory circuit by said read circuit;and a fifth routine of adding said third image data and said fifth imagedata to produce sixth image data by said third processing circuit. 14.The method as set forth in claim 13, wherein said fourth routine isoperated in parallel with said third routine.